Embedded configurable logic ASIC

ABSTRACT

An Application Specific Integrated Circuit (“ASIC”) ( 10, 30  and  40 ), which includes at least one hardware, non-programmable functional block ( 12, 14, 16, 18, 22, 32, 44, 46  and  48 ), also includes a programmable logic block (“PLB”) ( 26 ). The PLB ( 26 ) is electrically programmable for performing at least one function that complements a function performed using the hardware, non-programmable functional block ( 12, 14, 16, 18, 22, 32, 44, 46  and  48 ). The presence of the PLB ( 26 ) in the ASIC providing system builders with an opportunity to readily differentiate products within their respective product lines by adding particular functions to the ASIC, and to also functionally differentiate among various products offered by competing system builders.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to designing integrated circuits(“ICs”) and, more particularly, to the design of Application SpecificIntegrated Circuits (“ASICs”).

2. Description of the Prior Art

ASICs are used extensively throughout digital computers and other typesof electronic circuits. For example, ASIC System Logic Controller(“SLC”) ICs perform various functions essential to a digital computer'soperation including, in many instances, interfacing between a high-speedCPU bus and a slower speed Input/output (“I/O”) bus. Similarly, an ASICsuper I/O IC, which is coupled to a digital computer's slower speed I/Obus, provides one or more serial ports, one or more parallel ports, afloppy diskette drive controller, and an interface for an IntegratedDrive Electronics (“IDE”) hard disk drive. Via a Small Computer SystemInterface (“SCSI”) bus, ASICs also interface between a digital computersystem's bus and a peripheral device, such as a disk drive, a printer, ascanner, a tape drive, a CD ROM drive or an optical storage drive.Computer display controller cards; Video on Demand set-top boxes;communication network systems such as 10BaseT, 100BaseT and GigabitEthernet hubs, switches and routers; industrial embedded controllerssuch as those used in automobiles, process monitoring and control,portable and cellular telephones, games and household appliances; aswell as special purpose systems used to access the Internet all useASICs.

Because ASICs provide a truly cost-effective way of implementing a largenumber of digital logic circuits to perform a particular function, ASICdesigners and IC fabricators have developed certain techniques forreducing the difficulty, expense and time required to design and debugan ASIC, and to manufacture the ASIC in quantity. One technique tofacilitate implementing ASICs is known as a Gate Array. Using a GateArray, an ASIC designer merely specifies interconnections amongindividual digital logic circuits arranged in a pre-specifiedtwo-dimensional array of logic gates. Alternatively, a designer mayspecify an ASIC by selecting Standard Cells from among a library ofcells provided by an IC fabricator, specifying the location for StandardCells on an IC chip, and specifying interconnections among the selectedStandard Cells.

Because experience has established that ASICs are cost-effective, thenumber of circuits included in and the complexity of ASIC designsincreases year by year. Obviously, increasing ASIC complexity increasesthe likelihood of design errors in engineering prototypes, and alsoincreases the number of iterations required to obtain a design that iscommercially practical.

Moreover, not only are ASIC designs becoming ever more complex, ASICfabrication techniques are also advancing year by year. In theforeseeable future, ASIC geometry will decreases from 0.35 micronfeature size to 0.25 micron, 0.18 micron or even smaller feature size,while the size of IC wafers used for ASIC fabrication will concurrentlyincrease in diameter from 6 inches to 8 inches, and to 12 inches. Morecomplex ASIC designs will also require increasing the number ofmetalization layers from the 2 or 3 layers used at present to 5 or morelayers of metalization. Fabricating each layer of metalization requiresa different IC mask. The compounding effects of using ever smallerfeature size on ever larger diameter IC wafers with an increasing numberof metalization layers will significantly increase the Non-RecurringExpense (“NRE”) of ASIC design, debugging and development.

For example, in the future the price of masks used in ASIC fabricationwill increase from $2,000 per mask at present for 0.8 micron featuresize geometry on a 6 inch diameter wafer to $10,000 per mask for 0.35micron feature size geometry on an 8 inch diameter wafer. Consequently,because an average of seventeen (17) to thirty (30) masks will, ingeneral, be required to fabricate future ASICs, NRE for each engineeringprototype run will increase from $50,000 to $90,000 at present toperhaps $250,000 in the foreseeable future. An anticipated increase inwafer diameter from 8 inches to 12 inches will further increase the NREfor fabricating engineering prototypes.

Compounding all of the preceding technological considerations, that willsurely increase the NRE of ASIC engineering, is the business realitythat product life cycles continue to decrease. Traditional 4 to 8 weekturn-arounds for fabricating an ASIC engineering prototype combined with12 to 14 week lead times for ASIC production are becoming too long forproduct life cycles. Ever decreasing product life cycles in comparisonwith an ASIC's production cycle makes ASIC inventory control moredifficult. For example, a particular ASIC design may become obsoletebefore exhausting a conventional three month inventory of the ASICproduct.

There exist alternative ICs which digital logic designers may, in someinstances, substitute for an ASIC. These alternatives, some of which areknown as Field Programmable Gate Arrays (“FPGAs”), Programmable ArrayLogic (“PALs”),or Gate Array Logic (“GALs”), permit a digital logicdesigner to electronically program an IC to perform an applicationspecific digital logic function. Moreover, some of these devices areelectronically re-programmable, which, obviously, dramatically shortensthe time for, and expense of fabricating and debugging a prototype ASIC.Consequently, electronically creating an ASIC by merely programming astandard IC appears highly desirable in comparison with physicallymanufacturing an ASIC. Unfortunately, in many instances presentlyavailable programmable logic devices such as FPGAs, PALs and GALs proveexcessively expensive, particularly for high-volume products. Moreover,such ICs cannot, in general, provide a circuit density and/or circuitperformance comparable to those readily obtainable using ASICs, i.e.levels of circuit density and/or performance that are necessary toproduce a state-of-the-art product.

To address the preceding difficulties in ASIC prototype fabrication,Laser Programmable Gate Arrays (“LPGA”) have been developed whichpermits prototyping an ASIC in one day. However, LPGAs are suitable onlyfor low volume ASIC production, while mass production requiresconventional ASIC fabrication. Moreover, because a LPGA is a Gate Array,it cannot provide the circuit density of a conventional ASIC, nor can itachieve an ASIC's electrical performance. Moreover, laser ASICprototyping appears to require complicated, expensive, high-precisionprototyping equipment that must be located in a centralized facility towhich designs are transmitted for prototype fabrication. Finally, itappears that it will be difficult for laser prototyping to effectivelyand fully exploit the small feature size that foreseeable ASICs willemploy, or large number of devices which such ICs will provide. Thus,while ASIC prototype fabrication using LPGAs, in some instances, offersan improvement over conventional ASIC prototype fabrication, the NREstill remains costly in comparison with directly re-programmable FPGAS,PALs or GALS, and implementing an ASIC using a LPGA remains lessconvenient and more opaque to IC designers than directly programmabledevices.

To obviate the preceding difficulties in ASIC design U.S. Pat. No.5,687,325 discloses an application specific field programmable gatearray (“ASFPGA”) that includes at least two fixed functional units in asingle IC chip. Depending upon a specific application for the ASFPGA,the fixed functional units may include one or more bus interfaces, eventtimers, an interrupt controller, a Direct Memory Access (“DMA”)controller, system timers, a realtime clock, a Random Access Memory(“RAM”), a clock synthesizer, a RAM Digital-to-Analog Converter (“DAC”),a display interface, a register file, a compressed image encoder/decoder(“CODEC”), a micro-controller, or similar functional units. The ASFPGAalso includes a general purpose field programmable gate array (“FPGA”).The FPGA is configurable to effect a specific digital logic circuitinterconnection between fixed functional units. After the FPGA has beenconfigured, the fixed functional units together with the FPGA performall the functions specified for a particular ASIC design.

An alternative way of obviating the preceding difficulties, designers ofASICs have begun including pre-designed functional blocks in the ASICS.Presently functional blocks are available for ASIC design which includea Dynamic Random Access Memory (“DRAM”) block, a Static Random AccessMemory (“SRAM”) block, an Electronically Erasable Programmable Read OnlyMemory (“EEPROM”) block, a FLASH Memory block, a First-In/First-Out(“FIFO”) block, a Reduced Instruction Set Computer (“RISC”)microprocessor block, a Digital Signal Processor (“DSP”) block, businterface blocks such as an Industry Standard Architecture (“ISA”) businterface block, an Extended Industry Standard Architecture (“EISA”) businterface block, a Video Electronics Standards Association (“VESA”) businterface block, a Peripheral Component Interconnect (“PCI”) businterface block, a Universal Serial Bus (USB″), an Up/Down FrequencyConverter block, a Frequency-Hopping Spread-SpectrumModulator/Demodulator block, a Baseband Analog-to-Digital Converter(“ADC”) and DAC block, a Serial Data I/O (“SIO”) block, etc.

In developing an ASIC using functional blocks, designers seek to obtaindata specifying a particular functional block in at least four (4)different ways. First, a functional block to be employed in a new ASICdesign may be extracted from or re-used from a previous ASIC design. Ifa prior ASIC design lacks a particular functional block, the designermay sometimes obtain data specifying a needed functional block from thefoundry which will fabricate the ASIC. If previously developedfunctional blocks or functional blocks available from a foundry areinadequate for a particular ASIC design, the designer may seek tolicense a functional block's design data from some third party who hasalready developed and tested it. Lastly, if data specifying a suitablefunctional block design cannot be obtained in any of the three (3)preceding ways, then the ASIC designer may develop a functional blockspecifically for the ASIC. As is readily apparent, once a functionalblock has been developed as a last resort for a particular ASIC design,that functional block then becomes available for reuse in a subsequentASIC design.

While the use of functional blocks in ASIC design shortens the timerequired to develop and test a particular ASIC, the economies whichcompel the use of ASICs by system builders ultimately causes acommercial disadvantage for companies which purchase ASICs for assemblyinto systems. Because the functionality which systems assembled usingASICs is, to a significant extent, established by the functionalityinherent in the ASICs' designs, competing companies which assemblesystems using ASICs' experience difficulty in functionallydifferentiating among their respective competing products. That is, ifthe functionality inherent in the ASIC design controls or limits thefunctions that a system builder's product may provide, then systems fromvarious different competing companies will then all possess and offeressentially the same functionality. If systems from various differentcompeting companies all offer essentially the same function, the systembuilders can then compete primarily only on price and/or delivery.Consequently, system builders are always seeking ways in which they canfunctionally differentiate their products from those of theircompetitors even though the competing products are assembled usingessentially identical ASICs.

One way in which system builders seek to functionally differentiatetheir products from those of their competitors is through functionsprovided by software included in the system. While the functionalityprovided by computer programs can be readily changed or enhanced todifferentiate among competing systems, software can never provide systembuilders with complete freedom in differentiating among competingproducts because the performance provided by software functionality isgenerally several order of magnitude less than the performance which canbe achieved if the functionality is embedded into an ASIC.

This performance difference between hardware and software alsoexemplifies the fact that in designing any digital computer system therealways exist trade-offs between implementing a function in hardware orsoftware. That is a system designer is always free to choose toimplement a particular function in hardware, software, or a combinationof hardware and software. While implementing a particular function inhardware almost inevitably results in better performance, implementingthat function in hardware may require using a more expensive ASIC in thesystem which will ultimately result either in a higher price for thesystem, or reduced profit for the system builder. Thus, at presentselecting particular ASICs to be assembled into a digital computersystem essentially determines how system functionality is to bepartitioned between hardware and software. Once ASICs have been chosenfor a system, any functionality which the ASICs lack can be providedonly by the system's software. That is, there presently does not existany way system builders can enhance or add hardware functionality to anexisting system design other than by redesigning the system to usedifferent ASICs.

SUMMARY OF THE INVENTION

The present invention offers system builders an ability to functionallydistinguish between competing products.

An object of the present invention is to provide ASICs which permitssystem builders to functionally differentiate among products assembledusing essentially identical ASICs.

Another object of the present invention is to provide ASICs whichprovides enhanced flexibility in partitioning a system's overall designbetween hardware and software.

Briefly, the present invention is an ASIC that includes at least onehardware, non-programmable functional block which is adapted forperforming a function. The ASIC also includes a programmable logic block(“PLB”) that is electrically programmable for performing at least onefunction that complements a function performed by the hardware,non-programmable functional block.

The presence of the PLB in the ASIC provides system builders with anopportunity to readily differentiate products within their respectiveproduct lines by adding particular functions to the ASIC, and to alsofunctionally differentiate among various products offered by competingsystem builders. The PLB permits the system builder to implement inhardware, rather than in software, one or more functions that complementa system function that is performed using the hardware, non-programmablefunctional block included in the ASIC. As is readily apparent to thoseskilled in the art, implementing in hardware, rather than in software,one or more functions that complement a system function performed by thehardware non-programmable functional block produces a system thatexhibits improved performance. These and other features, objects andadvantages of the present invention will be understood or apparent tothose of ordinary skill in the art from the following detaileddescription of the preferred embodiment as illustrated in the variousdrawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram depicting an ASIC in accordancewith the present invention adapted for use as a PCI Bus Controller;

FIG. 2 is a functional block diagram depicting an ASIC in accordancewith the present invention adapted for use as a Smart Card Controller;and

FIG. 3 is a functional block diagram depicting an ASIC in accordancewith the present invention adapted for use as a RF Datacom IntegratedCircuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, depicted there is a block diagram of a PCI BusController (“PCIBC”) ASIC in accordance with the present invention thatis referred to by the general reference character 10. Conventionalfunctional blocks included in the PCIBC 10 include a SRAM block 12, anEEPROM or Flash Memory block 14, a FIFO block 16, a RISC processor orDSP block 18, and a PCI bus interface block 22. In principle, the RISCprocessor or DSP block 18 can be any type of central processing unit(“CPU”) including a DSP, a micro-controller, RISC or a complexinstruction set computer (“CISC”). Including the PCI bus interface block22 in the PCIBC 10 adapts it for connection to a PCI bus. However, thePCI bus interface block 22 could be replaced by an ISA bus interfaceblock which thereby adapting the controller for connection to an ISAbus. Alternatively, the PCI bus interface block 22 could be replaced bya USB or EISA bus interface block which thereby adapting the controllerfor connection to a USB or EISA bus. Identification and selection ofdata specifying specific functional blocks suitable for inclusion in thePCIBC 10, and the subsequent integration of such data into an operabledesign for the PCIBC 10 can be performed by those of ordinary skill inthe art of ASIC design.

In addition to the conventional functional blocks identified above thatare included in the PCIBC 10, the PCIBC 10 in accordance with thepresent invention also includes a PLB 26. Upon incorporating a PCIBC 10in accordance with the present invention into a system, presence of thePLB 26 in the PCIBC 10 provides system builders with an opportunity toreadily differentiate products within their own product lines by addingparticular functions to the PCIBC 10, and also functionallydifferentiate among various products offered by competitors. That is,the presence of the PLB 26 in the PCIBC 10 permits the system builder toimplement in hardware, rather than in software, one or more functionsthat complement a system function that is performed using at least oneof the functional blocks included in the PCIBC 10, i.e. SRAM block 12,EEPROM or Flash Memory block 14, FIFO block 16, RISC processor or DSPblock 18 and/or PCI bus interface block 22.

For example, in the instance of the PCIBC 10, the system builder couldprogram the PLB 26 to decode operations for a specific peripheral devicerather than performing such peripheral device decoding in operatingsystem software. As described above, a system which performs peripheraldevice decoding in hardware performs that function much more quicklythan a system which performs peripheral device decoding in software. Asis readily apparent, the presence of the PLB 26 in the PCIBC 10 thuspermits system builders to adapt systems functionally for specificoperating environments depending upon the particular function which thesystem builder chooses to program into the PLB 26 rather than havingthat function performed in software.

More specifically, customized logic 27, included in the PCIBC 10, isshared among certain application such as a media access controller(“MAC”), and address resolution logic (“ARL”), or DMA controller tomanage the data transmission, etc. Thus, including the PCIBC 10 in acomputer system permits the RISC processor or DSP block 18 to receivesignals from a modem, a telephone line, local area network (“LAN”), orany audio or digital signal input. The RISC processor or DSP block 18can then decode or process the received signals to convert them into aspecified format or sequence. After decoding or processing, the RISCprocessor or DSP block 18 stores the result either into the FIFO block16 which operates as a pipeline storage, or into a queue located in theSRAM block 12. In addition to providing storage for a queue, the SRAMblock 12 may also provide scratch pad storage for the RISC processor orDSP block 18. A CPU (not illustrated in any of the FIGS.), that isincluded in the computer system, communicates with the RISC processor orDSP block 18 through the PCI bus interface block 22. The EEPROM or FlashMemory block 14 provides non-volatile memory which can storeconfiguration data. In such a system designers could advantageously usethe PLB 26 to provide unique TCP/IP processing. An in-system programming(“ISP”) interface 28, included in the PLB 26, provides a port throughwhich the PLB 26 may be programmed or configured to implement suchTCP/IP processing.

FIG. 2 depicts a Smart Card Controller (“SCC”) ASIC in accordance withthe present invention that is referred to by the general referencecharacter 30. Those elements of the SCC 30 depicted in FIG. 2 that arecommon to the PCIBC 10 depicted in FIG. 1 carry the same referencenumeral distinguished by a prime (“′”) designation. The SCC 30 includesall of the same functional blocks as the PCIBC 10 except that aconventional functional SIO block 32 replaces the FIFO block 16. In theinstance of the SCC 30, functionality provided by the conventionalfunctional blocks would be complemented by adding a hardwareencryption/decryption function programmed into the PLB 26′.

The SIO block 32 provides a serial data link physical interface,indicated by arrowed lines 34, useful for protocols such as Token Ring,SDLC/HDLC etc. Included in the SCC 30, the RISC processor or DSP block18′ handles the protocols, instructions or data streams received throughthe SIO block 32. The customized logic 27′ handles particular tasks,which are common for different applications. The SRAM block 12′ can beused for temporary storage or as a scratch pad. The EEPROM or FlashMemory block 14′ stores configuration data. The PLB 26′ permits systembuilders to differentiate their respective implementations. Thus the PLB26′ may be used for encryption or decryption algorithms, managingvarious bus interfaces or devices, or displaying system status. Asdescribed for the PCIBC 10, the ISP interface 28′ permits programmingthe PLB 26′ to perform a desired function that facilitates serial datacommunication.

FIG. 3 depicts a RF Datacom Integrated Circuit (“RFDIC”) ASIC inaccordance with the present invention that is referred to by the generalreference character 40. Those elements of the RFDIC 40 depicted in FIG.3 that are common to the PCIBC 10 depicted in FIG. 1, or that are commonto the SCC 30 depicted in FIG. 2 carry the same reference numeraldistinguished by a double prime (“″”) designation. In addition to theconventional functional blocks of the SRAM block 12″, EEPROM or FlashMemory block 14″ and RISC processor or DSP block 18″, the RFDIC 40includes a conventional Up/Down Frequency Converter block 44, aconventional Frequency-Hopping Spread-Spectrum Modulator/Demodulatorblock 46, and a conventional Baseband ADC—DAC block 48. Thefunctionality provided by the conventional functional blocks of theRFDIC 40 would be complemented by programming TCP/IP protocolfunctionality into the hardware provided by the PLB 26″ rather thanproviding such functionality in software.

The RFDIC 40″ can be used wireless communications, such as mobilephones, GPS, personal communication systems (“PCS”), etc. The Up/DownFrequency Converter block 44″ provides a transceiver for wirelesstransmission and reception via an antenna 45. The Frequency-HoppingSpread-Spectrum Modulator/Demodulator block 46″ may be used to provideautomatic frequency locking and automatic gain control. TheFrequency-Hopping Spread-Spectrum Modulator/Demodulator block 46″ mayalso convert between a frequency transmitted from or received by theUp/Down Frequency Converter block 44″ and an intermediate frequency(“IF”), and modulate or demodulate the signal transmitted from orreceived by the Up/Down Frequency Converter block 44″. The RISCprocessor or DSP block 18″ may perform encoding, decoding, signalrecognition processing or synthesizing of the IF as required fordifferent protocols. The customized logic 27′ is common to variousapplications. The embedded SRAM block 12′ provides temporary storage orscratch pad. the EEPROM or Flash Memory block 14′ can storeconfiguration data. As indicated by an arrowed line 49, the BasebandADC—DAC block 48′ permits communication with Human Interface Devices(“HID”) that are external to the RFDIC 40 such as status displays,microphones, or video displays. For the RFDIC 40′, the PLB 26′ canfacilitate customizing security codes, types of communication services,or processing different protocols. Using the ISP interface 28′, the PLB26′ can be programmed to provide such customization, even remotely.

While there exist various alternative IC technologies which an ASICdesigner could select for the PLB 26, a PLB 26 in accordance with thepreferred embodiment of the present invention employs Programmable LogicDevice (“PLD”). PLD technology is preferred for the present inventionbecause it is simpler to use than FPGA technology. Furthermore, anyfunction programmed into the PLB 26 implemented with PLD technologyinherently possess predictable circuit timing characteristics.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is purely illustrative and is not to be interpreted aslimiting. For example, rather than using a re-programmable generalpurpose FPGA technology for interconnecting the various fixed functionallogic units of a ASIC in accordance with the present invention into afunctional ASIC, for production devices it may prove advantageous toemploy a write once digital programmable logic technology, such as a GALtechnology, rather than re-programmable FPGA technology. In production,after an ASIC has been fully developed, use of a re-programmabletechnology may be undesirable, and could even be disadvantageous.Accordingly, an ASIC in accordance with the present invention may employeither a re-programmable FPGA technology, or a write once programmabledigital logic technology. Consequently, without departing from thespirit and scope of the invention, various alterations, modifications,and/or alternative applications of the invention will, no doubt, besuggested to those skilled in the art after having read the precedingdisclosure. Accordingly, it is intended that the following claims beinterpreted as encompassing all alterations, modifications, oralternative applications as fall within the true spirit and scope of theinvention.

What is claimed is:
 1. In an application specific integrated circuit(“ASIC”) that includes at least one hardware, non-programmablefunctional block adapted for performing a function, an improvementcomprising: a programmable logic block (“PLB”) included in the ASIC,said PLB being electrically programmable for performing, during normaloperation of the ASIC, at least one function that complements thefunction performed using the hardware, non-programmable functionalblock.
 2. The ASIC of claim 1 wherein the hardware, non-programmablefunctional block is a bus interface block.
 3. The ASIC of claim 2wherein the bus interface block is an Industry Standard Architecture(“ISA”) bus interface block.
 4. The ASIC of claim 2 wherein the businterface block is an Peripheral Component Interconnect (“PCI”) businterface block.
 5. The ASIC of claim 2 wherein the bus interface blockis a Universial Serial Bus (“USB”) block^(˜).
 6. The ASIC of claim 1 theASIC is a PCI Bus Controller (“PCIBC”).
 7. The ASIC of claim 6 whereinthe hardware, non-programmable functional block of the PCIBC is aFirst-In/First-Out (“FIFO”) block, and a second hardware,non-programmable functional block included in the PCIBC is a processorblock.
 8. The ASIC of claim 7 wherein the processor block is a ReducedInstruction Set Computer (“RISC”) microprocessor.
 9. The ASIC of claim 1wherein the ASIC is a Smart Card Controller (“SCC”).
 10. The ASIC ofclaim 9 wherein the hardware, non-programmable functional block of theSCC is a Serial Data I/O (“SIO”) block, and the SCC includes a secondhardware, non-programmable functional block that is a processor block.11. The ASIC of claim 10 wherein the processor block is a RISCmicroprocessor.
 12. The ASIC of claim 1 wherein the ASIC is a RF DatacomIntegrated Circuit (“RFDIC”).
 13. The ASIC of claim 12 wherein thehardware, non-programmable functional block of the RFDIC is an Up/DownFrequency Converter block, and the RFDIC includes a second hardware,non-programmable functional block that is a processor block.
 14. TheASIC of claim 13 wherein the processor block is a Digital SignalProcessor (“DSP”).
 15. The ASIC of claim 12 wherein the hardware,non-programmable functional block of the RFDIC is a Frequency-HoppingSpread-Spectrum Modulator/Demodulator block, and the RFDIC includes asecond hardware, non-programmable functional block that is a processorblock.
 16. The ASIC of claim 15 wherein the processor block is a DSP.17. The ASIC of claim 12 wherein the hardware, non-programmablefunctional block of the RFDIC is a Base-band Analog-to-Digital Converter(“ADC”) and Digital-to-Analog (“DAC”) block, and the RFDIC includes asecond hardware, non-programmable functional block that is a processorblock.
 18. The ASIC of claim 17 wherein the processor block is a DSP.19. The ASIC of claim 17 wherein the processor block is a RISCmicroprocessor.
 20. An ASIC comprising: a hardware, non-programmablefunctional block which is adapted for performing a functions; and a PLBthat is electrically programmable for performing, during normaloperation of the ASIC, at least one function that complements a functionperformed by said hardware, non-programmable functional block.
 21. In aPCIBC ASIC that includes at least: a first hardware, non-programmableFIFO functional block; and a second hardware, non-programmable processorfunctional block; an improvement comprising: a PLB included in the ASIC,said PLB being electrically programmable for performing, during normaloperation of the ASIC, at least one function that complements thefunction performed using the hardware, non-programmable FIFO functionalblock.
 22. The ASIC of claim 21 wherein the processor block is a RISCmicroprocessor.
 23. In a SCC ASIC that includes at least: a firsthardware, non-programmable SIO functional block; and a second hardware,non-programmable processor functional block; an improvement comprising:a PLB included in the ASIC, said PLB being electrically programmable forperforming, during normal operation of the ASIC, at least one functionthat complements the function performed using the hardware,non-programmable SIO functional block.
 24. The ASIC of claim 23 whereinthe processor block is a RISC microprocessor.
 25. In a RFDIC ASIC thatincludes at least: a first hardware, non-programmable Up/Down FrequencyConverter functional block; and a second hardware, non-programmableprocessor functional block; an improvement comprising: a PLB included inthe ASIC, said PLB being electrically programmable for performing,during normal operation of the ASIC, at least one function thatcomplements the function performed using the hardware, non-programmableUp/Down Frequency Converter functional block.
 26. The ASIC of claim 25wherein the processor block is a DSP.
 27. In a RFDIC ASIC that includesat least: a first hardware, non-programmable Frequency-HoppingSpread-Spectrum Modulator/Demodulator functional block; and a secondhardware, non-programmable processor functional block; an improvementcomprising: a PLB included in the ASIC, said PLB being electricallyprogrammable for performing, during normal operation of the ASIC, atleast one function that complements the function performed using thehardware, non-programmable Frequency-Hopping Spread-SpectrumModulator/Demodulator functional block.
 28. The ASIC of claim 27 whereinthe processor block is a DSP.
 29. In a RFDIC ASIC that includes atleast: a first hardware, non-programmable Base-band ADC and DACfunctional block; and a second hardware, non-programmable processorfunctional block; an improvement comprising: a PLB included in the ASIC,said PLB being electrically programmable for performing, during normaloperation of the ASIC, at least one function that complements thefunction performed using the hardware, non-programmable Base-band ADCand DAC functional block.
 30. The ASIC of claim 29 wherein the processorblock is a DSP.
 31. The ASIC of claim 29 wherein the processor block isa RISC microprocessor.